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...the analog plus company TM
DS3/STS-1, E3 Integrated Line Transmitter
XR-T7296
June 1997-3
FEATURES D Fully Integrated Transmit Interface for DS3/STS-1 or E3 D Integrated Pulse Shaping Circuit D Compliance with Compatibility Bulletin 119 D Compliance with CCITT Recommendations G.703 & G.824 D Compliance with Bellcore TR-NWT-000499 D Compliance with ANSI T1.404 D Built-in B3ZS/HDB3 Encoder and Decoder D Remote and Local Loopback Functions D Single 5V Power Supply
APPLICATIONS D Interface for SONET, DS-3 and E3 Network Equipment D Digital Cross-Connect Systems D CSU/DSU Equipment D PCM Test Equipment D Fiber Optic Terminals
GENERAL DESCRIPTION The XR-T7296 is a fully integrated PCM Line Driver IC intended for DS3 (44.736Mbps) or E3 (34.368Mbps) applications. It can also be used for transmitting SONET STS-1 (51.84Mbps) signals over coaxial cable. The IC is designed to complement either XR-T7295 DS3/SONET STS-1 or XR-T7295E E3 Integrated Line Receivers. The XR-T7296 converts input clock and dual-rail unipolar data into AMI pulses according to AT&T Technical Advisory No. 34 or CCITT G.703 recommendations. The device provides B3ZS (DS3) or HDB3 (E3) encoding functions for data to be transmitted to the line. A complimentary decoder circuit is also included in the chip for decoding received signals from an external line receiver. Both encoder and decoder functions can be ORDERING INFORMATION
Part No. XR-T7296IP XR-T7296IW Package 28 Lead 600 Mil PDIP 28 J Lead 300 Mil JEDEC SOJ Operating Temperature Range -40C to + 85C -40C to + 85C
disabled independently through external control pins. In the receive direction, coding errors and bipolar violations are detected and flagged at an output pin. On-chip pulse shaper circuitry eliminates normally required external components for line equalization to meet the cross-connect template. For system level trouble-shooting and testing, both local and remote loop-backs are possible with the built-in loop-back circuit. The XR-T7296 is manufactured using BiCMOS technology and is packaged in a 28-pin PDIP or SOJ packages. The device requires a single 5V power supply and consumes a maximum power of 700mW. (Line current feed + device dissipation).
Rev. 2.01
E1992
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017 1
XR-T7296
BLOCK DIAGRAM
TAOS
5
ENCODIS
11
TXLEV
25
TPDATA TNDATA TCLK
AMP1
7 8 9
23
TTIP
B3ZS/HDB3 Encoder
Pulse Shaper
AMP2
22
TRING
Loop Back MUX RPDATA RNDATA RCLK
27 28
12 13 14 15 16
DECODIS BPV RNRZ RNEG RPOS RCLKO
1
B3ZS/HDB3 Decoder
DS3, STS-1/E3 MRING MTIP
4
17
19
Driver Monitor
20
18
DMO
2
3
6
10
21
24
26
RLOOP LLOOP
VDDD GNDD GNDA VDDA
ICT
Figure 1. XR-T7296 Block Diagram
Rev. 2.01 2
XR-T7296
PIN CONFIGURATION
RCLK RLOOP LLOOP DS3,STS-1/E3 TAOS VDDD TPDATA TNDATA TCLK GNDD ENCODIS DECODIS BPV RNRZ
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
RNDATA RPDATA ICT TXLEV VDDA TTIP TRING GNDA MTIP MRING DMO RCLKO RPOS RNEG
RCLK RLOOP LLOOP DS3,STS-1/E3 TAOS VDDD TPDATA TNDATA TCLK GNDD ENCODIS DECODIS BPV RNRZ
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
RNDATA RPDATA ICT TXLEV VDDA TTIP TRING GNDA MTIP MRING DMO RCLKO RPOS RNEG
28 Lead PDIP (0.600")
28 Lead SOJ (Jedec, 0.300")
PIN DESCRIPTION
Pin # 1 2 3 Symbol CLK RLOOP LLOOP Type I I I Description Receive Clock Input. Input sampling clock for RPDATA and RNDATA. Remote Loop Back. A high on this pin causes RPDATA and RNDATA to transmitted to the line using RCLK. Setting RLOOP and LLOOP high simultaneously is not permitted. Local Loop Back. A high on this pin causes TPDATA and TNDATA to pass through the encoder and output at RPOS and RNEG respectively. Setting LLOOP and RLOOP high simultaneously is not permitted. DS3, STS-1 or E3 Select Pin. A high on this pin selects DS3 or STS-1 operation and sets the encoder and decoder in B3ZS mode. A low selects E3 and sets the encoder and decoder in HDB3 mode. Transmit All Ones Select. A high on this pin causes a continuous AMI all 1's pattern to be transmitted to the line. The frequency is determined by TCLK. 5 V Digital Supply ($5%) for all logic circuitry. I I I I Transmit Positive Data. TPDATA is sampled on the falling edge of TCLK. Pin 7 and pin 8 can be tied together for binary input signals. Transmit Negative Data. TNDATA is sampled on the falling edge of TCLK. Pin 7 and pin 8 can be tied together for binary input signals. Transmit Clock for TPDATA and TNDATA. Digital Ground for all logic circuitry. Encoder Disable. A high on this pin disables B3ZS or HDB3 encoding functions, unless overridden by TAOS request. This pin must be set high if TPDATA and TNDATA are already encoded. Decoder Disable. A high on this pin disables B3ZS or HDB3 decoding functions.
4
DS3,STS-1/ E3 TAOS VDDD TPDATA TNDATA TCLK GNDD ENCODIS
I
5 6 7 8 9 10 11
I
12
DECODIS
I
Rev. 2.01 3
XR-T7296
PIN DESCRIPTION (CONT'D)
Pin # 13 Symbol BPV Type O Description Bipolar Violation Output. This pin goes high for one bit period when a bipolar violation not corresponding to the appropriate coding rule or coding error is detected in the RPDATA/ RNDATA signals. Receive Binary Data. Signal on this pin is the ORed-output of RPOS and RNEG. Receive Negative Data. This signal is the decoded version of RNDATA.1 Receive Positive Data. This signal is the decoded version of RPDATA.1 Receive Clock Output. This signal is the inverted version of RCLK. Driver Monitor Output. If no transmitted AMI signal is present on MTIP and MRING for 128 $32 TCLK clock periods. DMO goes high until the next AMI signal is detected. Monitor Ring Input. AMI signal from TRING can be connected to this pin for line driver failure detection. Internally pulled high. Monitor Tip Input. AMI signal from TTIP can be connected to this pin for line driver failure detection. Internally pulled high. Analog Ground for analog circuitry. O O I Transmit Ring Output. Transmit AMI signal is driven to the line via a 1:1 transformer from this pin. Transmit Tip Output. Transmit AMI signal is driven to the line via a 1:1 transformer from this pin. 5V Analog Supply ($5%) for analog circuitry. Transmit Level Select. The output signal amplitude at TTIP and TRING can be varied by setting this pin high or low. When the cable length is greater than 225 ft. TXLEV should be set high. When it is below 225 ft, it should be set low. This pin is active only with pin 4 set to DS3 or STS-1 mode. In-circuit Testing. A low at this pin causes all digital and analog outputs to go into a high-impedance state to allow for in-circuit testing. Internally pulled high. Receive Positive Data. NRZ input data to the decoder block. Sampled on the falling edge of RCLK. Receive Negative Data. NRZ input data of the decoder block. Sampled on falling edge of RCLK.
14 15 16 17 18 19 20 21 22 23 24 25
RNRZ RNEG RPOS RCLKO DMO MRING MTIP GNDA TRING TTIP VDDA TXLEV
O O O O O I I
26 27 28
ICT RPDATA RNDATA
I I I
Note 1 If a bipolar violation occurs, RPOS and RNEG can correspond to the decoded versions of RNDATA and RPDATA respectively. If DECODIS is high, RPOS and RNEG always track RPDATA and RNDATA respectively.
Rev. 2.01 4
XR-T7296
ELECTRICAL CHARACTERISTICS (See Figure 8 ) Test Conditions: VDD = 5V $5%, TA = -40C to +85C, unless otherwise specified. All timing characteristics are measured with 10pF loading.
Symbol AC Electrical Characteristics TCLK Clock Duty Cycle (DS3 / STS-1) TCLK Clock Duty Cycle (E3) tR tF tTSU tTHO tTDY tR tF tRSU tRHO tR tF tRDY TCLK Clock Rise Time (10% to 90%) TCLK Clock Fall Time (10% to 90%) TPDATA/TNDATA to TCLK Falling Set Up Time TPDATA/TNDATA to TCLK Falling Hold Time TTIP/TRING to TCLK Rising Propagation Delay 1 RCLK Clock Duty Cycle RCLK Clock Rise Time (10% to 90%) RCLK Clock Fall Time (10% to 90%) RPDATA/RNDATA to RCLK Falling Set Up Time RPDATA/RNDATA to RCLK Falling Hold Time RCLKO Clock Rise Time (10% to 90%) RCLKO Clock Fall Time (10% to 90%) RPOS/RNEG/RNRZ to RCLKO Rising Propagation Delay 2 DC Supply Voltage Supply Current 3 VIL VIH VOL VOH IL CI CL Input Low Voltage Input High Voltage Output Low Voltage IOUT=-4.0mA Output High Voltage IOUT=3.0mA Input Leakage Current 4 Pin 19/20/26 (Input=0V) Input Capacitance Load Capacitance -50 0 VDD* 0.7 GNDD VDDD - 0.5 4.75 5 4.0 5.0 4.0 4.0 4.0 4.0 5.0 0.6 45 50 14 55 4.0 4.0 45 47 50 50 55 53 4.0 4.0 % % ns ns ns ns ns % ns ns ns ns ns ns ns Parameter Min. Typ. Max. Units
DC Electrical Characteristics VDDD, VDDA 5.25 133 0.5 VDDD 0.4 VDDD $10 -150 10 10 V mA V V V V A A pF pF
Notes: 1 When the encoder is enabled, a handling delay of four and a half TCLK clock cycles for B3ZS and five and half clock cycles for HDB3 always exists between TPDATA/TNDATA and TTIP/TRING. The handling delay is reduced to two clock cycles when the encoder is disabled. 2 When the decoder is enabled, a handling delay of six and a half RCLK clock cycles will always exist between RPDATA/RNDATA and RPOS/RNEG/RNRZ. The handling delay is reduced to one and half RCLK clock cycles when the decoder is disabled. 3 Supply current is measured with transmitter sending all ones AMI signal and with Transmit Level (TXLEV) set to high. 4 All inputs except pin 19, 20 and pin 26.
Specifications are subject to change without notice
Rev. 2.01 5
XR-T7296
ABSOLUTE MAXIMUM RATINGS Power Supply . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +6.5V Storage Temperature . . . . . . . . . . . . . . -65C to 150C Voltage At Any Pin . . . . . . . . . . . . -0.5V to VDD +0.5V Power Dissipation SOJ Pkg. . . . . . . . . . . . . . . 725mW Power Dissipation DIP Pkg. . . . . . . . . . . . . . . . . . . . 1W Input Voltage (Any Pin) . . . . . . . . -0.5V to VDD + 0.5V Input Current (Any Pin) . . . . . . . . . . . . . . . . . . . . . 10mA
SYSTEM DESCRIPTION B3ZS/HDB3 ENCODER Data to be transmitted is input to the encoder block to be encoded either in B3ZS or HDB3 as determined by the state of the DS3,STS-1/E3 pin. Input data format can be unipolar or binary. For binary signals, TPDATA and TNDATA need to be connected together externally. The line code used for DS3 is B3ZS. In this mode, each block of three consecutive zeros is removed and replaced by one of two codes which contain bipolar violation. These replacement codes are B0V and 00V; where B indicates a pulse conforming with the bipolar rule and V represents a pulse violating the rule. The choice of these codes is made such that an odd number of B pulses will be transmitted between consecutive bipolar violation (V) pulses. For E3 format, the line code is HDB3. The encoding rule of HDB3 is similar to B3ZS except the number of consecutive zeros is increased to four before a code replacement can take place. The replacement codes in this case are 000V and B00V. STS-1 operation is achieved by placing the part in the DS3 mode and using 51.84 MHz clocks. Logic operation for STS-1 is the same for DS3. TRANSMIT ALL ONE SELECT Setting TAOS high causes continuous AMI encoded 1s to be transmitted to the line. In this mode, input TPDATA and TNDATA are ignored. If remote loop back (RLOOP) is set high, any TAOS request is ignored. REMOTE LOOP-BACK Setting RLOOP high causes receive RPDATA and RNDATA to be transmitted to the line through TTIP and TRING. The data rate is determined by RCLK. In this mode, TPDATA and TNDATA are ignored.
Rev. 2.01 6
LOCAL LOOPBACK Setting LLOOP high causes TPDATA and TNDATA to go through both the encoder and the decoder. In this mode, the transmit signal RCLKO, RPOS and RNEG corresponds to TCLK, TPDATA and TNDATA respectively. Unless overriden by TAOS request, TPDATA and TNDATA will still be transmitted to the line. Setting RLOOP and LLOOP high simultaneously is not permitted. B3ZS/HDB3 DECODER The decoder block is included to perform B3ZS or HDB3 decoding as determined by the state of the DS3, STS-1/E3 pin. In the B3ZS format, the decoder detects both B0V and 00V pulses and replaces them with 000 data. If HDB3 decoding is selected by setting the DS3, STS-1/E3 pin low, B00V and 000V pulses will be detected and replaced with 0000 code. In both cases, bipolar violation and coding errors which do not conform to the coding scheme are detected and indicated at the BPV output pin. DECODER DISABLE For testing purposes and in applications where the decoder needs to be bypassed, the decoder can be disabled by setting DECODIS high. In this mode all bipolar violation pulses are indicated at the BPV pin. BIPOLAR VIOLATION The BPV pin will go high for one bit period when a bipolar violation not corresponding to the appropriate coding rule or a code error is detected on the RPDATA/RNDATA. The violation pulse is always removed from the decoder output RPOS / RNEG when DECODIS is set low.
XR-T7296
PULSE SHAPER
TTIP
36$5%
1:1
75$5%
The pulse shaper circuit uses a combination of filters and slew rate control techniques to pre-shape the pulse going out to the line. The amplitude of the transmit pulse can be adjusted using the TXLEV (Transmit Level) pin. When the distance to the cross-connect exceeds 225 ft, TXLEV should be set high. When the distance is less than 225 ft. TXLEV should be set low. Setting TXLEV high enables the transmitter to send out a nominal voltage of 1.0V peak, and 850mV peak when low. The state of TXLEV pin has no effect on E3 operation.
TRING
36$5% 3
1
Note 1 Transformer = Pulse Engineering PE 65966, PE 65967 Surface Mount, Same Transformer for DS3, STS-1 and E3.
Figure 2. Transmit Pulse Amplitude Test Circuit Parameter Value 1:1 40H 1500Vrms 0.6H
DRIVER MONITOR Using TTIP and TRING as input, the driver monitor detects driver failure by monitoring the activities at MTIP and MRING. If no signal is detected on these pins for 128 TCLK cycles $32 cycles, DMO will be set high until the next AMI signal is detected.
Turn Ratio Primary Inductance Isolation Voltage Leakage Inductance
Table 1. Transmit Transformer Characteristics
Rev. 2.01 7
XR-T7296
DS3 SIGNAL REQUIREMENTS AT THE DSX For DS3 operation, pulse characteristics are specified at the DSX-3, which is an interconnection and test point referred to as the crossconnect. The crossconnect exists at the point where the transmitted signal reaches the distribution frame jack. The DSX-3 interconnection specification tables list the signal requirements (Table 1). The XR-T7296 can transmit through 450 feet of 782A cable to the DSX-3 in DS3 mode. Currently, two isolated pulse template requirements exist: the ANSI T1.404 pulse template (See Table 3 and Figure 3) and the Bellcore TR-NWT-000499 pulse template. The pulse transmitted by the XR-T7296 meets these templates.
Parameter Line Rate Line Code Test Load Pulse Shape 44.736Mbps $20 ppm
Specification Bipolar with three-0 substitution (B3ZS) 75 5% An isolated pulse must fit the template in Figure 3 or Figure 4.1 The pulse amplitude may be scaled by a constant factor to fit the template. The pulse amplitude must be between 0.36Vpk and 0.85Vpk, measured at the center of the pulse. For an all 1s transmitted pattern, the power at 22.368 $ 0.002MHz must be -1.8 to +5.7dBm, and the power at 44.736 $.002MHz must be -21.8dBm to -14.3dBm.2, 3
Power Levels
Notes
1
The pulse template proposed by G.703 standards is shown in Figure 4 and specified in Table 4 The proposed G.703 standards further state that the voltage in a time slot containing a 0 must not exceed 5% of the peak pulse amplitude, except for the residue of preceding pulses. 2 The power levels specified by the proposed G.703 standards are identical except that the power is to be measured in 3kHz bands. 3 The all 1s pattern must be a pure all 1s signal, without framing or other control bits.
Table 2. DSX-3 Interconnection Specification
Lower Curve Time T -0.36 -0.36 T +0.36 +0.36 T 0.5 [1 + Equation -0.03 sin/2 [1 +T/0.18 ]]-0.03 -0.03 Time T -0.68 -0.68 T + 0.36 +0.36
Upper Curve Equation +0.03 0.5[ 1 + sin/2 [1 +T/0.34]]+0.03 0.05+0.407e-1.84(T-0.36)
Table 3. DSX-3 Pulse Template Boundaries for ANSI T1.404 Standards (See Figure 3. )
Lower Curve Time -0.85 T -0.36 -0.36 T +0.36 +0.36 T +1.4 0.5 [1 + Equation -0.03 sin/2 [1 + T/0.18]] -0.03 -0.03 Time -0.85 T -0.68 -0.68 T + 0.36 -0.68 T 0.36
Upper Curve Equation +0.03 0.5[ 1 + sin/2 [1 +T/0.34]] +0.03 0.08+0.407e-1.84(T-0.36)
Table 4. DSX-3 Pulse Template Boundaries for Bellcore TR-NWT-000499 Standards (See Figure 4)
Rev. 2.01 8
XR-T7296
Normalized Amplitudes Normalized Amplitudes
1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 1.2 1.0 0.8 0.6 0.4 0.2 0.0
-01
-0.5
0
0.5
1.0
1.5
-0.2 -1.0
Time Slots-Normalized to Peak Location
Figure 3. DSX-3 Isolated Pulse Template for ANSI T1.404 Standards
Figure 4. DSX-3 Isolated Pulse Template for Bellcore TR-NWT-000499
Parameter Specification 51.84Mbps Bipolar with three-0 substitution (B3ZS) 75 5% A wide-band power level measurement at the STSX-1 interface using a lowpass filter with a 3dB cutoff frequency of at least 200MHz is within -2.7dBm and 4.7dBm.
STS-1 SIGNAL REQUIREMENTS For STS-1 operation, the cross-connect is referred at the STSX-1. Table 5 lists the signal requirements at the STSX-1. Instead of the DS3 isolated pulse template, an eye diagram mask is specified for STS-1 operation (TA-TSY-000253). (See Figure 5).
Line Rate Line Code Test Load Power Levels
Table 5. STSX-1 Interconnection Specification
1.2 Normalized Amplitude 1 0.3 0.6 0.4 0.2 0 -1.01 -0.2
-0.38
-0.18
0.03
0.24
0.45
0.65
0.86
1.07
-0.80
Figure 5. STSX-1 Isolated Pulse Template for Bellcore TA-TSY-000253
Rev. 2.01 9
-0.59
1.28
IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII
-0.5 0 0.5 1.0
IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII
1.5
Time Slots-Normalized to Peak Location
XR-T7296
E3 SIGNAL REQUIREMENTS The T7296 is designed to transmit pulses that conform to CCITT recommendation G.703. Figure 6 shows the E3 pulse mask requirement recommended in G.703, and Table 6 shows the pulse specifications.
V 0.2 0.1 1.0 0.1 0.2
17ns (14.55 + 2.45)
8.65ns (14.55 - 5.90)
Nominal pulse
14.55ns
0.5
12.1ns (14.55 - 2.45)
0.1 0 0.1
24.5ns (14.55 + 9.95) 0.2
0.1 0.1
29.1ns (14.55 + 14.55) CCITT-32581
Figure 6. CCITT G.703 Pulse Mark at the 34,368-kbit/s Interface
Parameter Pulse Shape (Nominally Rectangular)
Value All marks of a valid signal must conform with the mask (see Figure 6), irrespective of the sign One coaxial pair 75 resistive 1.0V 0V $ 0.1V 14.55ns 0.95 to 1.05 0.95 to 1.05
Pair(s) In Each Direction Test Load Impedance Nominal Peak Voltage of a Mark (Pulse) Peak Voltage of a Space (No Pulse) Nominal Pulse Width Ratio of the Amplitudes of Positive and Negative Pulses at the Center of a Pulse Interval Ratio of the Widths of Positive and Negative Pulses at the Nominal Half Amplitude
Table 6. E3 Pulse Specifications
Rev. 2.01 10
IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII
tR tRSU tF tRHO
IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII
tTDY tTSU tTHO
Rev. 2.01
RPOS/RNEG OR RNRZ TPDATA OR TNDATA RPDATA OR RNDATA TCLK TTIP OR TRING RCLKO RCLK tR tR
Figure 7. Timing Diagrams for System Interface
tRDY
11
tF tF
XR-T7296
XR-T7296
0
1
0
0
V
1
0
V
0
1
1
0
0
0
0
1
RPDATA RNDATA
V
RPOS RNEG RNRZ
0
1
0
0
0
1
0
1
0
1
1
0
0
0
0
1
BPV
BPV Corresponding To Coding Rule
BPV Not Corresponding To Coding Rule
Coding Error
Note The delay from RPDATA/RNDATA to RPOS/RNEG/RNRZ is not shown here.
Figure 8. Bipolar Violation Example for B3ZS Mode
Rev. 2.01 12
XR-T7296
VCC RI EC QT B 5 678
OUTPUTS RECEIVER MONITOR
S1 SW DIP-4
RLOS
RLOL
4321
L O S T H R
VCC
2134 5678 R22 22K
1357 TP TP R21 22K 24 6 8 19 18 17 14 15 16
U1 XR-T7295
INPUT SIGNAL B1 C2 8 7 2 RLOL RLOS RIN R2 75 EXTERNAL CLOCK B2 13 EXCLK R6 75 C3 0.1F 5 LPF2 V D D A 20 BT1 FERRITE BEAD C4 0.1F 0.1F V D D C V D D D C6 GNDC GNDD 4 LPF1 1 10 9 TMC1 TMC2 R5 0.01F LOSTHR REQB ICT/ RCLK RNDATA RPDATA
U2 XR-T7296
LLOOP R7 R8 R10 39 39 39 1 28 27 RLOOP DS3,STS-1/E3/ TAOS ICT/ TXLEV ENCODIS DECODIS 3 2 4 5 26 25 11 12
11111119 5 64 3 2 1 0 1 2 3 4 5 6 7 8
S2 16 15 14 13 12 11 10 9 LLOOP RLOOP T3/E3 TAOS TXLEV ICT ENCODIS DECODIS SW DIP-8
RCLK RNDATA RPDATA
P2 3 6 R1 50 GND
17 RCLKO 50 TCLK B5 9 TCLK RNEG RNRZ B4 TNDATA 8 TNDATA RPOS 16
RCLKO RPOS
GNDA
15 14
RNEG RNRZ
RECEIVER OUTPUTS
B3 TPDATA 7 TPDATA
TRING
22
R4
36
T1
B6
TTIP
11 21
TTIP MRING MTIP GNDD DMO 18 13 DMO BPV V D D A 24 V D D D BT2 6 GNDA
23 R15 19 20 10 21 R16 270 270
R3
36 PE65966
TRING
P1
TRANSFORMER # PULSE ENGINEERING PE 65966 PE 65967 IN SURFACE MOUNT
VCC RX C7 0.1F + E1 22F
BPV TRANSMITER MONITOR OUTPUTS
C8 0.1F
P3 VCC TX
FERRITE BEAD # FAIR RITE 2643000101
C9 0.1F
FERRITE BEAD
+E2 22F
C5 0.1F
Figure 9. Evaluation System Schematic
Rev. 2.01 13
XR-T7296
28 LEAD PLASTIC DUAL-IN-LINE (600 MIL PDIP)
Rev. 1.00
28
15 E1
1 D
14 E A2 A1
Seating Plane
A L B e B1
eA eB
C
INCHES SYMBOL A A1 A2 B B1 C D E E1 e eA eB L MIN 0.160 0.015 0.125 0.014 0.030 0.008 1.380 0.600 0.485 MAX 0.250 0.070 0.195 0.024 0.070 0.014 1.565 0.625 0.580
MILLIMETERS MIN 4.06 0.38 3.18 0.36 0.76 0.20 35.05 15.24 12.32 MAX 6.35 1.78 4.95 0.56 1.78 0.38 39.75 15.88 14.73
0.100 BSC 0.600 BSC 0.600 0.115 0.700 0.200
2.54 BSC 15.24 BSC 15.24 2.92 17.78 5.08 15
0 15 0 Note: The control dimension is the inch column
Rev. 2.01 14
XR-T7296
28 LEAD SMALL OUTLINE J LEAD (300 MIL JEDEC SOJ)
Rev. 1.00
D
28
15
E
1 14
H
A2 Seating Plane e B A1 C R E1
A
INCHES SYMBOL A A1 A2 B C D E E1 e H R MIN 0.145 0.025 0.120 0.014 0.008 0.697 0.292 0.262 MAX 0.200 --- 0.140 0.020 0.013 0.712 0.300 0.272
MILLIMETERS MIN 3.60 0.64 3.05 0.36 0.20 17.70 7.42 6.65 MAX 5.08 --- 3.56 0.51 0.30 18.08 7.62 6.91
0.050 BSC 0.335 0.030 0.347 0.040
1.27 BSC 8.51 0.76 8.81 1.02
Note: The control dimension is the inch column
Rev. 2.01 15
XR-T7296
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1992 EXAR Corporation Datasheet June 1997 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.01 16

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